Posted by : conceptedu in (Interview Questions)
SOFTWARE DESIGN
Tagged Under : C#, DOS, SOFTWARE DESIGN, VHDL
Frequently Asked Questions - Hardware & Software Design
Asked by a famous microprocessor manufacturer.
What is Finite Automata
What is a Turing machine?
How many processors are there in a pentium microprocessor?
In Sparc?
Difference between RISC and CISC
Is RISC always fast?
What is a real time system?
Name some real time OSs.
Is DOS a real time OS?
What is a kernel,shell?
What is binary search, traversal, hashing?
Write a code to count the no. of 1’s in a binary representation of
a number.
Memory taken for char *, int * etc.
char *cp;
int *ip;
cp++;
ip++;
What is the result?
Compare the no. of bytes in unix and Dos for long, char, short, int.
How do you make programs portable on unix and Dos under such
circumstances?
In C++, what is a constructor, destructor?
What is friend?
What is waterfall model, prototype model?
What is testing? What is unit testing, integration testing, etc?
What is indexing when talking about databases?
What is atomicity?
Can recursive programs be written in C++, Write a recursive program
to calculate factorial in C++.
What is best data structure to store the processes info in a real
time operating system?
Give two ways of converting a two input NAND gate to an inverter
Given a circuit, draw its exact timing response. (I was given a
Pseudo Random Signal Generator; you can expect any sequential ckt)
What are set up time & hold time constraints? What do they signify?
Which one is critical for estimating maximum clock frequency of a
circuit?
Give a circuit to divide frequency of clock cycle by two
Design a divide-by-3 sequential circuit with 50% duty circle.
(Hint: Double the Clock)
Suppose you have a combinational circuit between two registers
driven by a clock.What will you do if the delay of the combinational
circuit is greater than your clock signal? (You can’t resize the
combinational circuit transistors)
The answer to the above question is breaking the combinational
circuit and pipelining it. What will be affected if you do this?
What are the different Adder circuits you studied?
Give the truth table for a Half Adder. Give a gate level
implementation of the same.
Draw a Transmission Gate-based D-Latch.
Design a Transmission Gate based XOR. Now, how do you convert it
to XNOR? (Without inverting the output)
How do you detect if two 8-bit signals are same?
How do you detect a sequence of “1101″ arriving serially from a
signal line?
Design any FSM in VHDL or Verilog.
Explain RC circuit’s charging and discharging.
Explain the working of a binary counter.
Describe how you would reverse a singly linked list.
